1. Field of the Invention
This invention relates to resin sealed semiconductor devices, and more particularly to a structure of such devices having reduced mechanical stress caused by shrinkage of resins applied to elements formed near the sidewall surfaces of a major surface of a semiconductor substrate.
2. Description of the Background Art
FIG. 8 is a front sectional view of a conventional resin sealed semiconductor device. As shown in FIG. 8, a semiconductor chip 1 is soldered onto a die pad 2 of a metal plate. The semiconductor chip 1 includes an integrated circuit formed on the major surface of a semiconductor substrate, and a surface protecting film deposited thereon. External leads 3 are provided on both side surfaces of the semiconductor chip 1. Bonding pads 4 are provided near the sidewall surfaces of the major surface of the semiconductor chip 1, and the bonding pads 4 and the external leads 3 are electrically connected to each other by wires 5. The semiconductor chip 1, the die pad 2, portions of the external leads 3, the bonding pads 4 and wires 5 are all sealed with resin 6.
FIG. 9 is a plan view of this semiconductor device. As shown in FIG. 9, the semiconductor chip 1 is mounted on the surface of the die pad 2. A plurality of bonding pads 4 are formed near the sidewall surfaces of the major surface of the semiconductor chip 1. A plurality of external leads 3 are provided on both side surfaces of the semiconductor chip 1 and are electrically connected to the bonding pads 4 by the wires 5, respectively. The semiconductor chip 1, the die pad 2, the portions of the external leads 3, the bonding pads 4 and the wires 5 are all sealed with resin 6.
FIG. 10 is an enlarged view of a portion denoted by the arrow X in FIG. 9. This portion comprises a MOS (Metal Oxide Semiconductor) field effect transistor. A source region 8 and a drain region 9 are formed on the major surface of the semiconductor substrate 7. The source and drain regions 8 and 9 are formed by diffusion of n type or p type impurities in the major surface of the semiconductor substrate 7. The source region 8 is electrically connected to an aluminum interconnection layer 15 through a contact hole. The drain region 9 is electrically connected to an aluminum interconnection layer 16 through the contact hole. A gate electrode 10 made of polysilicon is formed on a channel forming region between the source and drain regions 8 and 9. The end portion of the gate electrode 10 is electrically connected to an aluminum interconnection layer 17 through the contact hole. The aluminum interconnection layer 17 is electrically connected to the bonding pad 4 formed of aluminum. Patterning of deposited aluminum forms the bonding pad 4 and the aluminum interconnection layer 17. Thus, the bonding pad 4 and aluminum interconnection layer 17 are formed at the same time, and the bonding pad 4 and the external lead 3 are electrically connected to each other by the wire 5. Field oxide films 11a and 11b which are insulating films for isolation, are formed with the source and drain regions 8 and 9 sandwiched therebetween, the field oxide films being positioned on a portion of the major surface of the semiconductor substrate 7 other than the source and drain regions 8 and 9.
FIG. 11 is a cross sectional view of the semiconductor device taken along the line XI--XI of FIG. 10. As shown in FIG. 11, the semiconductor substrate 7 is mounted on a major surface of the die pad 2. The field oxide films 11a and 11b are formed on a major surface of the semiconductor substrate 7, and a thin gate oxide film 12 is formed between the field oxide films 11a and 11b. The gate electrode 10 is formed on the field oxide films 11a and 11b and on the gate oxide film 12. An interlayer insulating film 13 made of a phospho-silicate glass is deposited on the gate electrode 10. A contact hole 18 is formed in the interlayer insulating film 13 on the end portion of the gate electrode 10. The aluminum interconnection layer 17 is formed on the interlayer insulating film 13. The aluminum interconnection layer 17 and the gate electrode 10 are electrically connected to each other through aluminum filling the contact hole 18. A passivation film 14 is deposited on the interlayer insulating film 13 and on the aluminum interconnection layer 17. The passivation film 14 serves as a surface protecting film.
As a method of sealing a semiconductor chip, two methods are employed: one is sealing with a resin and the other is hermetic sealing with a ceramic package or the like. Since the resin is less expensive than the ceramic package, the method of sealing the semiconductor chip with the resin is more widely used.
For the resin sealed semiconductor device, however, it is known that mechanical stress caused by shrinkage of resin is applied to a semiconductor element, resulting in deterioration in the electrical characteristics of the semiconductor element. This will now be described with reference to the results of an experiment.
This experiment was carried out by employing a MOS capacitor formed on a TEG (Test Element Group) chip. The TEG chip has a semiconductor substrate on which elements and interconnections are formed. An example of application of the TEG chip will be described. Before application of a MOS transistor of a new size to the semiconductor device, the MOS transistor is previously formed on the TEG chip to carry out tests of reliability. After reliability of the MOS transistor can be confirmed, the MOS transistor becomes applicable in practice to the semiconductor device.
FIG. 12 is a sectional view of the MOS capacitor formed on the TEG chip. The MOS capacitor 27 has a p type silicon substrate 21, a thin oxide film 23 formed on this substrate, and an electrode 24 of polysilicon formed on the thin oxide film 23. Field oxide films 22a and 22b are formed on both end portions of the thin oxide film 23.
An electrode 25 made of aluminum is formed on one end portion of the electrode 24 made of polysilicon. The p type silicon substrate 21 is grounded. A current source 26 is connected to the aluminum electrode 25, and its minus (-) connected to the aluminum electrode 25 and its plus (+) grounded.
Two types of the TEG chips are prepared: a resin sealed TEG chip having the aforementioned MOS capacitor and a non-sealed TEG chip without resin having the aforementioned MOS capacitor. A continuous flow of current through the MOS capacitor formed on each of the TEG chips causes electric stress to be applied to the MOS capacitor and thus makes a flat band voltage of the MOS capacitor to shift by a predetermined amount. The flat band voltage is a voltage to be applied to a gate electrode in order to make a surface electric field at an interface between the gate oxide film and semiconductor substrate decrease to zero. As the flat band voltage of a MOS capacitor is shifted, electrical characteristics of the MOS capacitor deteriorate.
The conditions of flat band voltage shifted are described with reference to FIG. 13, which is a graph showing a C-V characteristic of a given MOS capacitor. The ordinate C indicates a capacitance, while the abscissa V indicates a voltage, in the graph. The curve denoted with reference number 91 represents the relationship between the capacitance and voltage of the MOS capacitor before electric stresses are applied to the MOS capacitor. The curve denoted with reference number 92 represents the relationship between the capacitance and voltage of the MOS capacitor after electric stresses are applied to the MOS capacitor. The capacitance is varied in a certain range of voltage displacement with respect to both the curves 91 and 92. The flat band voltage is within this range of voltage displacement. Assuming that the flat band voltage before electrical stresses are applied is denoted with a, and the flat band voltage after electrical stresses are applied is denoted with b, the amount of shifting the flat band voltage is expressed as .DELTA.V=b-a.
The time required for shifting the flat band voltage is measured at constant current densities of 10 pA/cm.sup.2, 20 pA/cm.sup.2 and 40 pA/cm.sup.2, respectively. The amount of the flat band voltage to be shifted is all the same at the respective values of the constant current densities. The constant current density is a value obtained by division of a constant current by the area of portions of the polysilicon electrode 24 on the thin oxide film 23. It is assumed that the time required for shifting a predetermined amount of the flat band voltage in the MOS capacitor of the no-resin sealed TEG chip is 100 at a constant current density of 10 pA/cm.sup.2.
FIG. 14 is a graph showing the result of the experiment. The dotted line indicates the result of the experiment of the MOS capacitor of the no-resin sealed TEG chip, while the solid line indicates that of the MOS capacitor of the resin sealed TEG chip. As shown in FIG. 14, the MOS capacitor of the no-resin sealed TEG chip requires a longer period of time to shift the flat band voltage than the MOS capacitor of the resin sealed TEG chip at a constant current density lower than 40 pA/cm.sup.2. As described above, shifting of the flat band voltage deteriorates the electrical characteristics of the semiconductor elements. Therefore, the electrical characteristics of the resin sealed semiconductor device deteriorate more rapidly than those of the hermetic sealed semiconductor device.
In the resin sealed semiconductor device, the electrical characteristics of the elements formed near the sidewall surfaces of the major surface of the semiconductor substrate deteriorate more rapidly than those of the elements formed in the middle of the major surface of the semiconductor substrate. This results from the fact that the mechanical stress caused by sealing with a resin is applied from the directions of the upper surface, the lower surface and the side surface of the semiconductor substrate 7, as shown by the arrows A in FIG. 11. The mechanical stress applied from above and below the substrate is applied uniformly onto all the elements formed on the major surface of the semiconductor substrate. On the other hand, the mechanical stress applied from the sides of the substrate is more heavily concentrated on the elements at the sidewall surfaces of the semiconductor substrate, than the elements in the middle of the major surface of the semiconductor substrate. Therefore, greater mechanical stress is applied to the elements at the sidewall surfaces of the major surface of the semiconductor substrate than those in the middle of the major surface of the semiconductor substrate. As a result, the electrical characteristics of the elements in the sidewall surfaces of the major surface of the semiconductor substrate deteriorate more rapidly than those of the elements in the middle of the major surface of the semiconductor substrate.
Particularly, the elements located within 100 .mu.m from the sidewall surface of the semiconductor substrate have their electrical characteristics rapidly deteriorated by the mechanical stress. Since elements are formed within 100 .mu.m from the edges of the semiconductor substrate due to high integration of the semiconductor device, the deterioration of the electrical characteristics of the semiconductor elements due to the mechanical stress is a major problem.